The Shift Register is a 4 position memory of sorts. A bit is loaded from the DATA input at a logical “high” signal at the CLOCK input and appears at the Q0 output. At the next high Clock signal the bit is shifted from Q0 to Q1 and a new bit is loaded in to Q0 from DATA. When a bit reaches Q3 it is shifted out of the register. This functions as a delay on a 1-Bit datastream, where the CLOCK determines delay. If the outputs are combined with an XOR gate, an outline is achieved.
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Listed2 months ago
ConditionExcellent (Used)
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  • Castle 011 Shift Register
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  • United States

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La Puente, CA, United States
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